Field of the Invention
The present invention relates to a semiconductor manufacturing method, and more specifically, relates to a plasma processing method and apparatus for forming gate electrodes having a metal gate/high-k structure, a step structure and a three-dimensional structure that demands high selectivity with respect to the underlayer film and mask layer and also demands perpendicular processing.
Description of the Related Art
In MOSFET (metal-oxide-semiconductor field-effect transistor) devices used in digital appliances, personal computers and cellular phones, for example, there are continuous demands for improvement in integration, speed and function. In order to cope with these demands, miniaturization of the prior-art Poly-Si/SiO2 structure has been promoted, along with studies for discovering gate electrodes with a new structure and formed of new materials.
According to the principles of dry etching processes used for forming gate electrodes of planar MOSFET and FIN-FET having such metal gate/high-k structure, plasma is generated from reactive gases via electromagnetic waves, and ion assisted reaction is caused by the generated ions and neutral radicals. Therefore, the plasma processing apparatus for performing the above-described method includes a plasma generating mechanism, a reactive gas supplying mechanism, a pressure control mechanism, a lower electrode mechanism for placing the Si wafer, a Si wafer transfer mechanism, and a mechanism for controlling the operation timings or the like of each mechanism. The lower electrode mechanism is further composed of an electrostatic chuck mechanism for holding the Si wafer, a temperature control mechanism for the Si wafer, and a bias supplying mechanism.
In the method for controlling an ion energy distribution function (IEDF) using a plasma processing apparatus having mechanisms mentioned above, the waveforms and frequencies of the bias being supplied are known to influence the process. For example, Japanese Patent Application Laid-Open Publication No. 2002-141341 (patent document 1) discloses a method for supplying a pulse-like bias and a method for supplying a dual frequency bias having a low frequency of 25 kHz or lower and a high frequency of 2 MHz or higher, in order to improve the etching selectivity with respect to Si when etching a dielectrics. It is further disclosed in Journal of Vacuum Science and Technology A Volume 20 p. 1759 (non-patent document 1) that the frequency output by the bias mechanism has an IEDF depending on the time required to pass through the plasma sheath.
On the other hand, Japanese Patent Application Laid-Open Publication No. 2007-250755 (patent document 2) discloses a monitor for detecting the state of plasma, by which the voltage, current and phase of the high frequency waves are monitored to detect defects such as the insulation degradation of the inner walls of the chamber or the insulating film of the lower electrode.
When a multilayered metal gate/high-k gate electrode having an STI step 310 as shown in FIG. 3A is dry-etched in a prior-art plasma processing apparatus, it was difficult to simultaneously prevent underlayer penetration 312 of the high-k gate dielectrics and prevent the occurrence of a footing 314 so as to achieve a perpendicular bottom shape. Similar drawbacks related to underlayer selectivity, perpendicular processing and isolated-dense shape differences caused by the sparseness and denseness of the wiring disposed on the substrate are even more crucial in the etching of FIN-FET gates. Etched feature profile differences such as the underlayer penetration at the upper portion of the step of the FIN with a size of approximately 50 nm, the side-etch of the upper portion of the gate length portion or the footing formed at the bottom portion become the cause of the variation of CMOS performance.